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NInput Voltage Range : 2.5V ~ 20V NOutput Voltage Range : 2.5V ~ 16V (Fixed Voltage Type) : 30V + (Adjustable Type) NOscillation Frequency Range : 100kHz ~ 600kHz NOutput Current : up to 1.5A NCeramic Capacitor Compatible NMSOP-8A Package
GMobile, Cordless phones GPalm top computers, PDAs GPortable games GCameras, Digital cameras GLaptops
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GStable Operations via Current & Voltage Multiple Feedback GUnlimited Options for Peripheral Selection GCurrent Protection Circuit GCeramic Capacitor Compatible
The XC9101 series are step-up multiple current and voltage feedback DC/DC controller ICs. Current sense, clock frequencies and amp feedback gain can all be externally regulated. A stable power supply is possible with output currents of up to 1.5A. With output voltage fixed internally, VOUT is selectable in 0.1V steps within a 2.5V - 16.0V range ( 2.5%). For output voltages outside this range, we recommend the FB version which has a 0.9V internal reference voltage. Using this version, the required output voltage can be set-up using 2 external resistors. Switching frequencies can also be set-up externally within a range of 100~600 kHz and therefore frequencies suited to your particular application can be selected. With the current sense function, peak currents (which flow through the driver transistor and the coil) can be controlled. Soft-start time can be adjusted using external resistor and capacitor. During shutdown (CE pin =L), consumption current can be reduced to as little as 0.5A (TYP.) or less.
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GOrdering Information
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XC9101C33AKR
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XC9101C50AKR
PARAMETER Output Voltage Maximum Operating Voltage Minimum Operating Voltage Supply Current 1 0.95V Supply Current 2 Set Output Voltage 1.05V Stand-by Current CLK Oscillation Frequency Frequency Input Stability w e e w SYMBOL CONDITIONS UNITS CIRCUITS q q q w
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Frequency Temperature Fluctuation Maximum Duty Cycle Minimum Duty Cycle Current Limiter Voltage Current CE "High" Current CE "Low" Current CE "High" Voltage Existence of CLK Oscillation, V CE "Low" Voltage EXT "High" ON Resistance EXT "Low" ON Resistance Efficiency Soft-Start Time CC/GAIN Pin Output Impedance
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Disappearance of CLK Oscillation, =0V, CE : Voltage applied
r V =Set voltage 0.95V r V =Set voltage 1.05V q Connect C and R , CE : 0V 3.0V q u
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XC9101D09AKR
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XC9101C33AKR
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NMOS Coil Resistor : XP161A1355PR : 22H(CR105 SUMIDA) : 20m for Isen (NPR1 KOA), 33k(trimmer) for CLK, 100k for SS 47F(OS)+220F(any) for CL, 220F(any) for CIN SD : U3FWJ44N (TOSHIBA) Capacitors : 180pF(ceramic) for CLK, 470pF(ceramic) for CC/GAIN, 0.1F(ceramic) for SS,1F(ceramic) for Bypass
XC9101C50AKR
NMOS Coil Resistor
: XP161A1355PR : 22H(CR105 SUMIDA) : 20m for Isen (NPR1 KOA), 33k(trimmer) for CLK, 100k for SS 47F(OS)+220F(any) for CL, 220F(any) for CIN
Capacitors : 180pF(ceramic) for CLK, 470pF(ceramic) for CC/GAIN, 0.1F(ceramic) for SS,1F(ceramic) for Bypass SD : U3FWJ44N (TOSHIBA)
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XC9101D09AKR
NMOS Coil Resistor
: XP161A11A1PR : 22H(CDRH127 SUMIDA) : 10m for Isen (NPR1 KOA), 33k(trimmer) for CLK, 150k for SS 47F(OS)+220F(any) for CL, 220F(any) for CIN
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Capacitors : 180pF(ceramic) for CLK, 470pF(ceramic) for CC/GAIN, 0.1F(ceramic) for SS,1F(ceramic) for Bypass SD VOUT RFB1 RFB2 CFB VOUT RFB1 RFB2 CFB : U5FWJ44N (TOSHIBA) : 16V : 560k : 33k : 27pF : 20V : 470k : 22k : 33pF
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Step-up DC/DC converter controllers of the XC9101 series carry out pulse width modulation (PWM) according to the multiple feedback signals of the output voltage and coil current. The internal circuits consist of different blocks that operate at VIN or the stabilized power (2.0 V) of the internal regulator. The output setting voltage of the type C controller and the FB pin voltage (Vref = 0.9 V) of type D controller have been adjusted and set by laser-trimming.

With regard to clock pulses, a capacitor and resistor connected to the CLK pin generate ramp waveforms whose top and bottom are 0.7V and 0.15V, respectively. The frequency can be set within a range of 100 to 600 kHz externally (refer to the "Functional Settings" section for further information). The clock pulses are processed to generate a signal used for synchronizing internal sequence circuits.

The Verr amplifier is designed to monitor the output voltage. A fraction of the voltage applied to internal resistors R1, R2 in the case of a type C controller, and the voltage at the FB pin in the case of a type D controller, are fed back and compared with the reference voltage. In response to feedback of a voltage lower than the reference voltage, the output voltage of the Verr amplifier increases. The output of the Verr amplifier enters the mixer via resistor (RVerr). This signal works as a pulse width control signal during PWM operations. By connecting an external capacitor and resistor through the CE/GAIN pin, it is possible to set the gain and frequency characteristics of Verr amplifier signals (refer to the "Functional Settings" section for further information).
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The Ierr amplifier monitors the coil current. The potential difference between the VIN and Isen pins is sampled at each switching operation. Then the potential difference is amplified or held, as necessary, and input to the mixer. The Ierr amplifier outputs a signal ensuring that the greater the potential difference between the VIN and Isen pins, the smaller the switching current. The gain and frequency characteristics of this amplifier are fixed internally.

The mixer modulates the signal sent from Verr by the signal from Ierr. The modulated signal enters the PWM comparator for comparison with the sawtooth pulses generated at the CLK pin. If the signal is greater than the sawtooth waveforms, a signal is sent to the output circuit to turn on the external switch.

The current flowing through the coil is monitored by the limiter comparator via the VIN and Isen pins. The limiter comparator outputs a signal when the potential difference between the VIN and Isen pins reaches about 150 mV or more. This signal is converted to a logic signal and handled as a DFF reset signal for the internal limiter circuit. When a reset signal is input, a signal is output immediately at the EXT pin to turn off the MOS switch. When the limiter comparator sends a signal to enable data acceptance, a signal to turn on the MOS switch is output at the next clock pulse. If at this time the potential difference between the VIN and Isen pins is large, operation is repeated to turn off the MOS switch again. DFF operates in synchronization with the clock signal of the CLK pin.

The soft start function is made available by attaching a capacitor and resistor to the CE/SS pin. The Vref voltage applied to the Verr amplifier is restricted by the start-up voltage of the CE/SS pin. This ensures that the Verr amplifier operates with its two inputs in balance, thereby preventing the ON-TIME signal from becoming stronger than necessary. Consequently, soft start time needs to be set sufficiently longer than the time set to CLK. The start-up time of the CE/SS pin equals the time set for soft start (refer to the "Functional Settings" section for further information). The soft start function operates when the voltage at the CE/SS pin is between 0V to 1.55V. If the voltage at the CE/SS pin doesn't start from 0V but from a mid level voltage when the power is switched on, the soft start function will become ineffective and the possibilities of large rush currents and ripple voltages occuring will be increased.
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GFunctional Settings 1. Soft Start
CE and soft start (SS) functions are commonly assigned to the CE/SS pin. The soft start function is effective until the voltage at the CE pin reaches approximately 1.55 V rising from 0 V. Soft start time is approximated by the equation below according to values of Vcont, Rss, and Css. T = -Css x Rss x ln((Vcont - 1.55)/Vcont) Example: When CSS = 0.1 F, RSS = 470 k, and Vcont = 5 V, T = -0.1 e-6 x 470 e3 x ln ((5 - 1.55)/5) = 17.44 ms.
Set the soft start time to a value sufficiently longer than the period of a clock pulse.
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> Circuit example 1: N-ch open drain
> Circuit example 2: CMOS logic (low current dissipation)
> Circuit example 3: CMOS logic (low current dissipation), quick off
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2. Oscillation Frequency
The oscillation frequency of the internal clock generator is approximated by the following equation according to the values of the capacitor and resistor attached to the CLK pin. To stablize the IC's operation, set the oscillation frequency within a range of 100kHz to 600kHz. Select a value for Cclk within a range of 150pF to 220pF and fix the frequency based on the value for Rclk. f = 1/(-Cclk x Rclk x ln0.26) Example: When Cclk = 220 pF and Rclk = 10 k, f = 1/(-220e-12 x 10e3 x ln(0.26)) = 337.43 kHz.
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3. Gain and Frequency Characteristics of the Verr Amplifier
The gain at output and frequency characteristics of the Verr amplifier are adjusted by the values of the capacitor and resistor attached to the CC/GAIN pin. It is generally recommended to attach a CC of 220 to 1,000 pF without RGAIN. The greater the CC value, the more stable the phase and the slower the transient response. When using the IC with RGAIN connected, it should be noted that if the RGAIN resistance value is too high, abnormal oscillation may occur during transient response time. The size of RGAIN should be carefully evaluated before connection.
4. Current Limit
The current limit value is approximated by the following equation according to resistor RSEN inserted between the VIN and Isen pins. Double function, current FB input and current limiting, is assigned to the Isen pin. The current limiting value is approximated by the following equation according to the value for RSEN. Ilpeak_limit = 0.15/Rsen Example: When RSEN = 100 m, Ilpeak_limit = 0.15/0.1 = 1.5 A
The inside error ampliphier sends feedback signal when the voltage occurs at RSEN resisitors because of the flow of coil current in order to phase compensate. The more the RSEN value becomes larger, the more the error signal becomes bigger, and it could lead to an intermittent oscillation. Please be careful if there is a problem with the application. When the regular operation, the voltage which occurs between RSEN resistors because of coil peak should be set lower than the current limit voltage of 90mV (min.). For more details, please refer the notes on the external components.
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5. FB Voltage and Cfb
With regard to the XC9101D series, the output voltage is set by attaching externally divided resistors. The output voltage is determined by the equation shown below according to the values of Rfb1 and Rfb2. In general, the sum of Rfb1 and Rfb2 should be 1 MEG or less. VOUT = 0.9 x (Rfb1 + Rfb2)/Rfb2 The value of Cfb (phase compensation capacitor) is approximated by the following equation according to the values of Rfb1 and fzfb. The value of fzfb should be 10 kHz, as a general rule. Cfb = 1/(2 x x Rfb1 x fzfb) Example: When Rfb1 = 455 k and Rfb2 = 100 k : VOUT = 0.9 x (455 k + 100 k)/100 k = 4.995 V : Cfb = 1/(2 x x 455 k x 10 k) = 34.98 pF
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GApplication Notes
1. The XC9101 series are designed for use with an output ceramic capacitor. If, however, the potential difference between input and output is too large, a ceramic capacitor may fail to absorb the resulting high switching energy and oscillation could occur on the output side. If the input-output potential difference is large, connect an electrolytic capacitor in parallel to compensate for insufficient capacitance. 2. The EXT pin of the XC9101 series is designed to minimize the through current that occurs in the internal circuitry. However, the gate drive of external PMOS has a low impedance for the sake of speed. Therefore, if the input voltage is high and the bypass capacitor is attached away from the IC, the charge/discharge current to the external PMOS may lead to unstable operations due to switching operation of the EXT pin. As a solution to this problem, place the bypass capacitor as close to the IC as possible, so that voltage variations at the VIN and VSS pins caused by switching are minimized. If this is not effective, insert a resistor of several to several tens of ohms between the EXT pin and PMOS gate. Remember that the insertion of a resistor slows down the switching speed and may result in reduced efficiency. 3. A PNP transistor can be used in place of PMOS. If using a PNP transistor, insert a resistor (Rb) and capacitor (Cb) between the EXT pin and the base of the PNP transistor in order to limit the base current without slowing the switching speed. Adjust Rb in a range of 500 to 1 k according to the load and hFE of the transistor. Use a ceramic capacitor for Cb, complying with Cb 1/(2 x x Rb x Fosc x 0.7), as a rule.
4. Although the C_CLK connection capacitance range is from 150 ~ 220pF, the most suitable value for maximum stability is around 180pF.
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GRecommended Pattern Layout
q In order to stablize VDD's voltage level, we recommend that a by-pass capacitor (CDD) be connected as close as possible to the VIN & VSS pins. w In order to stablize the GND voltage level which can fluctuate as a result of switching, we suggest that C_CLK's, R_CLK's & C_GAIN's GND be separated from Power GND and connected as close as possible to the VSS pin (by-pass capacitor, CDD). Please use a multi layer board and check the wiring carefully. Pattern Layout Examples
XC9101D Series
2 Layer Evaluation Board
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1 Layer Evaluation Board
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GNotes Ensure that the absolute maximum ratings of the external components and the XC9101 DC/DC IC itself are not exceeded. We recommend that sufficient counter measures are put in place to eliminate the heat that may be generated by the external N-MOSFET as a result of switching losses. Try to use a N-MOSFET with as small a gate capacitance as possible in order to avoid overly large output spike voltages that may occur (such spikes occur in proportion to gate capacitance). The performance of the XC9101 DC/DC converter is greatly influenced by not only its own characteristics, but also by those of the external components it is used with. We recommend that you refer to the specifications of each component to be used and take sufficient care when selecting components. Wire external components as close to the IC as possible and use thick, short connecting wires to reduce wiring impedance. In particular, minimize the distance between the by-pass capacitor and the IC. Make sure that the GND wiring is as strong as possible as variations in ground potential caused by ground current at the time of switching may result in unstable operation of the IC. Specifically, strengthen the ground wiring in the proximity of the VSS pin.
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XC9101D09AKR (1) OUTPUT VOLTAGE vs. OUTPUT CURRENT
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(2) EFFICIENCY vs. OUTPUT CURRENT
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(3) RIPPLE VOLTAGE vs. OUTPUT CURRENT
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Note : If the difference between the input and output voltage is large or small, switching ON / OFF time will be shortened. As such, the external components used and their values ( inductance value of the coil, resistor connected to CLK, capacitor etc. ) may have a critical influence on the actual operation of the IC.
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